module aru_reduce (
    input logic                 clk,
    input logic                 rst_n,
          aru_reduce_cfg_if.in  u_aru_cfg_if,
          aru_payload_if.in     u_aru_payload_if,
          aru_reduce_pld_if.out u_aru_reduce_pld_if
);

    // ==================== 内部接口声明 ====================
    // 配置接口
    aru_reduce_ctrl_if u_aru_ctrl_transpose_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_ctrl_if u_aru_ctrl_stage1_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_ctrl_if u_aru_ctrl_stage2_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_ctrl_if u_aru_ctrl_stage3_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_ctrl_if u_aru_ctrl_div_if (
        .clk  (clk),
        .rst_n(rst_n)
    );

    // 数据通路接口
    aru_reduce_pld_if u_transpose_to_stage1_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_pld_if u_stage1_to_stage2_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_pld_if u_stage2_to_stage3_if (
        .clk  (clk),
        .rst_n(rst_n)
    );
    aru_reduce_pld_if u_stage3_to_div_if (
        .clk  (clk),
        .rst_n(rst_n)
    );

    // ==================== 配置流水线模块 ====================
    aru_reduce_cfg_pipe u_cfg_pipe (
        .clk                      (clk),
        .rst_n                    (rst_n),
        .u_aru_cfg_if             (u_aru_cfg_if),
        .u_aru_reduce_transpose_if(u_aru_ctrl_transpose_if),
        .u_aru_reduce_stage1_if   (u_aru_ctrl_stage1_if),
        .u_aru_reduce_stage2_if   (u_aru_ctrl_stage2_if),
        .u_aru_reduce_stage3_if   (u_aru_ctrl_stage3_if),
        .u_aru_reduce_div_if      (u_aru_ctrl_div_if)
    );

    // ==================== Transpose模块 ====================
    aru_reduce_transpose u_transpose (
        .clk                (clk),
        .rst_n              (rst_n),
        .u_aru_ctrl_if      (u_aru_ctrl_transpose_if.in),
        .u_aru_payload_if   (u_aru_payload_if),
        .u_aru_reduce_pld_if(u_transpose_to_stage1_if.out)
    );

    // ==================== Stage1模块 ====================
    aru_reduce_stage1 u_stage1 (
        .clk                      (clk),
        .rst_n                    (rst_n),
        .u_aru_ctrl_if            (u_aru_ctrl_stage1_if.in),
        .u_aru_reduce_transpose_if(u_transpose_to_stage1_if.in),
        .u_aru_reduce_stage1_if   (u_stage1_to_stage2_if.out)
    );

    // ==================== Stage2模块 ====================
    aru_reduce_stage2 u_stage2 (
        .clk                   (clk),
        .rst_n                 (rst_n),
        .u_aru_ctrl_if         (u_aru_ctrl_stage2_if.in),
        .u_aru_reduce_stage1_if(u_stage1_to_stage2_if.in),
        .u_aru_reduce_stage2_if(u_stage2_to_stage3_if.out)
    );

    // ==================== Stage3模块 ====================
    aru_reduce_stage3 u_stage3 (
        .clk                   (clk),
        .rst_n                 (rst_n),
        .u_aru_ctrl_if         (u_aru_ctrl_stage3_if.in),
        .u_aru_reduce_stage2_if(u_stage2_to_stage3_if.in),
        .u_aru_reduce_stage3_if(u_stage3_to_div_if.out)
    );

    // ==================== Div模块 ====================
    aru_reduce_div u_div (
        .clk                   (clk),
        .rst_n                 (rst_n),
        .u_aru_ctrl_if         (u_aru_ctrl_div_if.in),
        .u_aru_reduce_stage3_if(u_stage3_to_div_if.in),
        .u_aru_reduce_div_if   (u_aru_reduce_pld_if)
    );

endmodule
